As semiconductor device circuit density increases and device feature size decreases, increased numbers of patterned metal levels are required with decreased spacing between metal lines at each level to effectively interconnect discrete semiconductor devices on semiconductor chips. The different levels of metal interconnections are separated by layers of insulating materials or films, often referred to as inter-level dielectric (ILD) layers. These interposed insulating layers have etched holes or trenches that are filled with a conductive material, referred to as vias or plugs, which are used to connect one level of metallization lines to the next. A common insulating material used for ILD layers is silicon oxide (SiO2), which has a dielectric constant (k) of about 4.0 to 4.5, relative to a vacuum, which has a k value of 1.0.
However, as semiconductor device dimensions decrease and the packing density increases, it is necessary to reduce the spacing between the metal lines at each level of interconnection to wire up the integrated circuits. Unfortunately, as the spacing decreases, the intra-level and inter-level capacitances increase between metal lines, as capacitance is inversely proportional to the spacing between the lines. Therefore, it is desirable to minimize the dielectric constant k of the insulating material (dielectric) between the conducting lines, in order to reduce the RC time constant and thereby increase the performance of the circuit, e.g., the frequency response, since the signal propagation time in the circuit is adversely affected by the RC delay time.
To achieve an insulating layer with a dielectric constant of 3 or less, low-k insulating films are often used for ILD layers. However, lower-k dielectric materials usually have poor mechanical strength and related properties. In general, the lower the k value, the poorer the mechanical strength. Introducing low-k insulating materials into a multi-level metallization integration scheme results in a mechanically weak and vulnerable low-k interconnect stack, degrading the reliability of the semiconductor device and resulting in device failures.